CAD/EDA Silicon Design/Verification Infrastructure Engineer

Position Title: CAD/EDA Silicon Design/Verification Infrastructure Engineer
Location: Santa Clara, CA
Term: Possible 3-Month Contract-to-Hire (CTH)

Job Description: We are seeking a CAD/EDA Silicon Design/Verification Infrastructure Engineer with strong experience in SoC/IP design and verification infrastructure. The ideal candidate will have hands-on expertise in Python, SystemVerilog/UVM, and working in Linux-based environments.

Minimum Qualifications:

• 5 years of experience in EDA/CAD for SoC/IP design or verification infrastructure.
• Intermediate to advanced proficiency in Python 3.x (must be demonstrated through work experience).
• Solid understanding of ASIC/SoC flows, SystemVerilog, and UVM.
• Hands-on experience with Linux development tools (shell scripting, Makefiles, etc.).

Key Responsibilities:

• Contribute to integration testing and top-level functionality of subsystems with multiple processors (ARM/RISC) and Networks-on-Chip (NoC)
• Perform UVM-based SoC verification
• Read and write C code for basic test development, compilation, and hex generation for processor tests
• Conduct verification tasks involving concurrency and memory access scenarios
• Define and implement SoC verification plans
• Build test benches for sub-system and SoC-level verification
• Develop and execute functional tests based on the test plan
• Track coverage and drive design verification to closure using defined metrics (functional, code, test plan coverage)
• Debug and root-cause functional failures in collaboration with the design team
• Work cross-functionally with Design, Modeling, Emulation, and Silicon Validation teams to ensure high design quality
• Continuously improve design verification methodologies and tools