Sr. ASIC Design Engineer - RTL, PCIe, CXL

Job Title: Sr. ASIC Design Engineer - RTL, PCIe, CXL

Job Location: San Jose, CA

Compensation: $175K - $225K base Depending on experience plus stock options!

Requirements: RTL Design, ASIC Design, Microarchitecture, PCIe, CXL

We were founded in 2020 by a team of veterans in Silicon Valley, and our mission is to accelerate AI computing in data centers and HPC by introducing high-performance, power efficient, scalable and cost-effective interconnect solutions. AI computing and data center architectures are undergoing a fundamental transformation of disaggregation and composability, driven by the enablement of CXL (Computing Express Link) technology.

We are working on a CXL/PCIe-based chip for cloud computing applications. We're expanding our team and looking to add a Sr. ASIC Design Engineer.

Top Reasons to Work with Us

• Competitive Compensation ($175K - $225K base Depending on Experience)
• Comprehensive Benefits package including stock options!
• The chance to join a small start-up tackling challenging problems with huge upside potential!
  
  

What You Will Be Doing

• Participate in architecture definition and modeling.
• Contribute to micro-architecture specification and reviews.
• Review industry standard specs and ensure IPs are kept up to date for compliance.
• Define design partitioning for efficient IP/sub-system/full chip implementation.
• Review and provide feedback on verification plans and methodology.
• Drive block/chip/system level development and execution.
• Work with Hard IP designers, verification, validation, Firmware engineers, and architects to produce thoroughly verified, robust IP.
• Actively participate in post-silicon bring-up, validation and compliance testing.
  
  

What You Need for this Position

Preferred

Must have a Bachelor's (Master's or Ph.D. preferred) in Computer Science, Electrical Engineering, Computer Engineering, or similar with 10 - 15 years of experience:

• 10 - 15 years of experience in logic design using Verilog/System Verilog
• Very strong domain knowledge about PCIe/CXL
• Proven track record of taking several chips in from product definition to production.
• Experience in complex ASIC design.
• Good understanding of ASIC design and verification methodologies and flows.
• Architecture/Micro-architecture definition
• Design partitioning and Hard IP interactions
• Multiple async clock domain designs
• Design for test
• Clock/Reset
• Power-aware
• Excellent understanding of Synthesis, STA, CDC, Lint, LEC
• Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
• Proficient in Perl scripting
  
  

So, if you are a Sr. ASIC Design Engineer with PCIe and/or CXL experience, please apply today! or send an updated copy of your resume to Mike.Vandenbergh@CyberCoders.com for immediate consideration!

Email Your Resume In Word To

Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply, but you may also:

mike.vandenbergh@cybercoders.com

• Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : MV1-1754862 -- in the email subject line for your application to be considered.***
  
  

Mike Vandenbergh - Lead Recruiter

For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa.

CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.

This job was first posted by CyberCoders on 07/19/2023 and applications will be accepted on an ongoing basis until the position is filled or closed.

CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at Benefits@CyberCoders.com to make arrangements.