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Sr. Silicon Design Engineer, ASIC, RTL, IP

Advanced Micro Devices, Inc
San Jose, CA Full Time
POSTED ON 2/24/2026
AVAILABLE BEFORE 5/27/2026


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




 

THE ROLE: 

We are looking for an adaptive, self-motivatived senior silicon design engineer to join our growing AI team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading AI technologies to market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. 

 

THE PERSON: 

You have a passion for modern, complex architecture and digital design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Digital design implementation and micro-architecture
  • RTL coding in Verilog/SystemVerilog
  • Design flow quality checks - Lint, CDC, RDC, LCP and others
  • Timing closure - timing constraints, synthesis, logic-depth reduction 
  • Design area optimizations
  • Low power design techniques, UPF included
  • Sub-system and IP Integration into SoC
  • Physical Design support
  • Hardware modeling support

 

PREFERRED EXPERIENCE: 

  • Several years of working experience in ASIC design
  • Proficiency in Verilog/SystemVerilog RTL 
  • Active knowledge of ASIC design quality flows
  • Communication bus protocols - AXI or similar
  • Design tools including Spyglass, Questa CDC, Conformal, VCS, Verdi, DVE
  • Front-end design of multi-clock / multi-reset domain blocks
  • Low power analysis and design
  • Shell/Tcl/Perl/Python scripting skills
  • Version control systems such as Perforce, ICManage

 

ACADEMIC CREDENTIALS: 

  • Bachelor's or master's degree in computer engineering/Electrical Engineering 

 

#LI-MV1

#HYBRID




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Salary.com Estimation for Sr. Silicon Design Engineer, ASIC, RTL, IP in San Jose, CA
$144,230 to $164,256
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