What are the responsibilities and job description for the Formal Verification Engineer position at Canvendor?
We do have a Formal Verification Engineer role in San Jose, CA (onsite). Please find the Job Description below and kindly respond back with your updated resume.
Job Title : Formal Verification Engineer
Job Location : San Jose, CA (onsite)
Duration : 12 Months
Job Description:
We are seeking a highly skilled and motivated Formal Verification Engineer to join our hardware design and verification team. In this role, you will be responsible for applying formal methods to verify the correctness of digital designs, ensuring they meet functional specifications and industry standards. You will collaborate closely with design, verification, and architecture teams to deliver robust, high-quality products.
Key Responsibilities
- Develop and execute formal verification plans for complex digital designs (e.g., SoCs, IP blocks, ASICs, FPGAs).
- Write and maintain formal properties and assertions using industry-standard languages (e.g., SystemVerilog Assertions, PSL).
- Analyze and debug counterexamples, root-cause failures, and work with designers to resolve issues.
- Integrate formal verification into the overall verification flow, complementing simulation-based approaches.
- Collaborate with design and verification engineers to define verification strategies and coverage goals.
- Document verification results, methodologies, and best practices.
- Stay current with advancements in formal verification tools and methodologies.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Solid understanding of digital design concepts, RTL design (Verilog/VHDL), and computer architecture.
- Hands-on experience with formal verification tools (e.g., JasperGold, Questa Formal, OneSpin, Synopsys VC Formal).
- Proficiency in writing formal properties/assertions (SVA, PSL, or similar).
- Strong analytical and problem-solving skills.
- Excellent communication and teamwork abilities.
Preferred Qualifications
- Experience with simulation-based verification (UVM, SystemVerilog).
- Familiarity with scripting languages (Python, Perl, Tcl) for automation.
- Prior experience in processor, memory, or interface IP verification
