What are the responsibilities and job description for the Formal Verification Engineer position at ACL Digital?
Job Title: Formal Verification Engineer
Location: San Jose, CA or Austin, TX
Duration: Contract
Looking for an experienced formal verification engineer with hands-on experience on development of FPV, DPV, AEP & SEQ setups and system Verilog assertion expertise.
Requirements:
- Must have experience in Formal Verification (Min 3 years)
- Develop formal verification setup using System Verilog modules and Assertions
- Run formal verification checks, analyze the results, and debug any issues.
- Develop and enhance constraints, checks, and cover points to achieve verification quality
- Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions
