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Senior ASIC / RTL Design Engineer
$130k-148k (estimate)
Full Time
1 Week Ago
Cynet Systems is Hiring a Senior ASIC / RTL Design Engineer Near San Jose, CA
Job Description:
Pay Range $50.64hr - $75.97hr
Pay Range $50.64hr - $75.97hr
- The work will expose the designer to a number of IP including Client cores, Ethernet, DDR, DMA, PCIE, SATA and client internal IP.
- Successful candidates will be responsible for leading, and participating in, the design of leading-edge SoC s in advanced digital CMOS processes.
- RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
- SoC Design.
- Knowledge AND hand-on experience from industry ASIC design flow including RTL coding, IP Integration, debugging/verification, and supporting synthesis and timing closure.
- Working knowledge of Client cores and other I/O standard interfaces.
- Roughly 10 years experience, but less is acceptable.
- An ideal candidate would also exhibit.
- Strong communication and documentation skills, Good organizational, time management and multitasking skills.
- Strong initiative and discipline to follow-through, Technical leadership.
Job Summary
JOB TYPE
Full Time
SALARY
$130k-148k (estimate)
POST DATE
05/04/2024
EXPIRATION DATE
05/20/2024
WEBSITE
cynetsystems.com
HEADQUARTERS
ARCOLA, VA
SIZE
500 - 1,000
FOUNDED
2010
CEO
ASHWANI MAYUR
REVENUE
$50M - $200M
INDUSTRY
IT Outsourcing & Consulting
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