Sr. Digital Design Verification Engineer

Direct Hire

FTE, Full Benefits... Hybrid, Onsite Cambridge, MA

Security Requirement:

The ability to obtain a US secret clearance is required which requires proof of US citizenship Active secret clearance is preferred

Digital Design Team is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.

You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

Duties and Responsibilities:

Develop verification and test plans Develop UVM Agents for proprietary buses Instantiate VIPs for industry standard buses Work in both block-level/chip-level UVM testbench environment Work with RTL designers to resolve simulation issues Implement cover groups according to design requirements Work on code and functional coverage closures to achieve 100% Perform code reviews and to mentor junior engineers in the group

Required Qualifications:

BS degree with 8 years experience Fluent in SystemVerilog including SVA Recent experience with UVM/UVMF Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS) Familiarity with at least one IEEE bus standard Experience with DDR3/DDR4 Firm grasp of constrained-random testing and coverage-driven verification Experience with formal analysis Practice using Python, Perl, Bash or other scripting languages Ability to work in a Linux environment Strong analysis and problem-solving skills