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Reporting to Sr. Manager ASIC Engineering, as a Senior ASIC Verification Engineer, you will:

• Develop test benches and tests for FPGAs and ASICs.

• Assist in root-causing RTL bugs.

• Develop verification models.

• Draft detailed test plans.

• Partaking in test plan and coverage analysis of the block and SOC-level verification.

The Must Haves:

• Bachelor / Master or PhD degree in Electrical Engineering coupled with proven experience in ASIC development with Verilog.

• Experience with ASIC design verification, synthesis, timing/power analysis and DFT.

• Minimum 5 years of work experience is required in ASIC Verification, including proficiency in UVM and System Verilog.

• Strong debug and lab experience.

Assets:

• Knowledge of high-performance and low-power design techniques.

• Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.

• Experience with modern SoC design architectures, ARM/MiPs type processor cores, Ethernet, Networking, and Data Communications.

• Knowledge of assertion-based formal verification.

• Proficient with a scripting language like Perl.

*California Salary Range: $ 147,800 - $ 236,200

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Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

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