We are seeking an experienced and highly skilled Silicon Verification Engineer to join our dynamic team. The ideal candidate will have a robust background in ASIC design and verification, with a strong proficiency in SystemVerilog and UVM methodologies. You will be responsible for ensuring the functionality and performance of our silicon products through rigorous verification processes and collaboration with cross-functional teams.

Responsibilities:

• Develop comprehensive test plans and coverage models to ensure thorough verification of silicon designs.
• Utilize transaction level modeling, pseudo and constrained random techniques, and assertion-based/formal verification techniques.
• Define and develop unit and IP/SoC level test benches using SystemVerilog.
• Implement UVM verification environments, including the creation of agents and scoreboards.
• Document and execute test plans by developing tests, test generators, test benches, checkers, and coverage models.
• Execute tests on RTL and Gate Level Netlists.
• Debug failures to root cause and provide recommendations for fixes.
• Drive regression health through triage, coverage analysis, and advanced simulation debug techniques.
• Manage pre- and post-silicon verification test flows.
• Support the creation and maintenance of automated test benches.
• Collaborate with design and product teams to support post-silicon verification activities.
• Assist in the validation of silicon products through hands-on testing and analysis.
• Work effectively within diverse and inclusive teams.
• Communicate verification status, issues, and solutions clearly and efficiently to stakeholders.

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8 years of experience in ASIC design, verification, or a related field.
• Proven track record in defining and developing test benches using SystemVerilog.
• Extensive experience with VMM/OVM/UVM methodologies.
• Strong understanding of test-plan generation, coverage analysis, and various verification techniques.
• Proficient in developing and implementing UVM verification environments.
• Ability to run tests and debug at both RTL and Gate Level.
• Experience with pre- and post-silicon verification processes and automated test benches.

Top Skills Required:

1. Proficient in defining and developing unit and IP/SoC level test benches using SystemVerilog and VMM/OVM/UVM (5 YOE)
2. Experience with high-Speed Serial or wide parallel interfaces such as D2D, Ethernet/PCIe/USB or DDDR PHY IPs (5 YOE)
3. Analog and Mixed-signal IP's such as ADC's, Bandgaps, Power Regulators (5 YOE)
4. Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes (5 YOE)

About Brickred Systems:

Brickred Systems is a global leader in next-generation technology, consulting, and business process service companies. We enable clients to navigate their digital transformation. Brickred Systems delivers a range of consulting services to our clients across multiple industries around the world. Our practices employ highly skilled and experienced individuals with a client-centric passion for innovation and delivery excellence.