ASIC/RTL Design Engineer

Job Title: ASIC/RTL Design Engineer

Work Location: Santa Clara, CA 95054

Duration: 12 Months

Work Type: Temporary Assignment

Job Type: Hybrid

Pay rate: $70.00-$70.00/Hr

Overview:

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Job Description:

THE ROLE:

• We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team.
• As a key contributor, you will be part of a leading team to drive and improve client's abilities to deliver the highest quality, industry-leading technologies to market.
• Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:

• You have a passion for modern, complex processor architecture, digital design, and verification in general.
• You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones.
• You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Top Must Have Skills:

• Solid minimum 8 years Design Verification Experience
• Verification Experience with DDR5 Controller /PHY
• System Verilog /UVM - Language Skills

KEY RESPONSIBILITIES:

• Develop/Maintain tests for functional verification.
• Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Work on functional & code coverage verification.
• Provide technical support to other teams

PREFERRED EXPERIENCE:

• Experience with C/C
• Experience with Verilog, System Verilog, and modern verification libraries like UVM
• 10 years of ASIC design verification experience
• Experience / Background with DDR or Memory Controller. PHY Verification is a plus
• Experience with scripting languages like Python, Perl and TCL is a plus.
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Understanding of Design for Test methodologies and DFT verification experience is a plus
• Proficient in debugging firmware and RTL code using simulation tools

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in computer engineering/Electrical Engineering

TekWissen® Group is an equal opportunity employer supporting workforce diversity.