What are the responsibilities and job description for the HW Characterization/Test Developer position at Technical Link?
Job Details
Role Description: As an ASIC Library Characterization Engineer, you will help deliver an ASIC chip to be used on quantum systems. You will be responsible for developing, validating, and maintaining digital and analog/mixed-signal IP libraries used in ASIC design flows. This role involves deep technical engagement with the characterization process, including timing, power, and functional modeling, and requires hands-on experience with EDA tools and scripting to build and maintain custom flows. Unlike roles that rely on turnkey solutions, this position demands expertise in the internals of library development and flow automation.
Minimum Qualifications:
- BS/MS in Computer Engineering, Electrical Engineering, or related.
- 5 years in ASIC library characterization or physical design
- Proficiency in Cadence Virtuoso and Innovus
- Proficiency in scripting languages (e.g. Python, Tcl, Perl, Bash, SKILL)
- Proficiency in Verilog/SystemVerilog preferred. VHDL acceptable.
- Technical skills including:
- Hard macro abstract/LEF generation and maintenance
- Liberty file format familiarity
Preferred Qualifications:
- Contributions to flow development, automation, and optimization
- Experience with timing, noise, and power integrity analysis
- Technical skills including:
- Analog/mixed-signal IP hardening
- Verilog model generation for analog/mixed-signal IP
- Constraint description for analog/mixed-signal IP
- DFT view generation and maintenance
Responsibilities:
- Characterize standard cells and analog/mixed-signal IP for timing, power, and noise
- Generate and maintain Liberty (.lib) files and abstract views
- Develop and maintain DFT views and Verilog models for IP blocks
- Create and validate constraints for analog/mixed-signal IP
- Automate library characterization flows using scripting languages
- Collaborate with the design team to integrate libraries into full-chip flows
- Debug and resolve issues in timing, power, and abstraction views
- Ensure high-quality deliverables for tape-out readiness
Salary : $70 - $100
