What are the responsibilities and job description for the STA Engineer position at Sintegra Inc.?
STA / Timing Implementation Engineer (PCIe Focus)
Role Overview We are seeking a Timing Implementation Engineer with strong expertise in Static Timing Analysis (STA) and constraint development for high-speed interfaces such as PCIe. This role is focused on implementation and timing closure, not design, and requires hands-on experience driving block-level and full-chip timing sign-off from RTL synthesis through tapeout.
Key Responsibilities
- Perform block-level and full-chip STA throughout the project lifecycle, from early investigation to final tapeout.
- Write and develop timing constraints for PCIe and other high-speed interfaces.
- Build and enhance timing methodology and infrastructure to support flows from RTL synthesis to implementation and closure.
- Collaborate with architects and logic designers to generate accurate block and chip-level timing constraints.
- Define analysis scenarios and margining strategies with system and technology teams.
- Partner with physical design teams to achieve timing closure and ensure robust silicon sign-off.
Minimum Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
- 5 years of industry experience, with at least 3 years focused on STA and timing closure.
- Hands-on expertise with Synopsys PrimeTime or equivalent STA tools.
- Proven experience writing and debugging timing constraints (SDC) for PCIe or other high-speed protocols.
- Strong collaboration skills with physical design and architecture teams.
Preferred Qualifications
- Experience with multi-clock domain designs, CDC analysis, and power-aware STA.
- Familiarity with advanced process nodes (7nm and below).
- Knowledge of timing ECO flows and sign-off methodologies.
- Exposure to high-speed interfaces (PCIe, DDR, SerDes) and their timing requirements.