What are the responsibilities and job description for the RF/Analog IC Designer position at Ripple Technology Inc.?
Ripple Technology is working on WiFi 6/7 AP SOC and looking to bring on a RF/Analog IC Designer to join our team in the Bay Area.
Design radio transceiver blocks, such as PA, LNA, mixer, TIA, LPF, VGA, ADC/DAC, etc.Design LO blocks, such as crystal oscillator, RF synthesizer, LO distribution network.Design Analog blocks, such as Bandgap, POR, LDO, DC-DC converter, Low power clock, power detector, ESD, test mux, etc.Guide layout engineer to do the layout, and able to do the critical layout individually with DRC/LVS/xRC.Work with the team to define the block specs, doing link budget analysis, noise, linearity, phase noise, SNR, and EVM optimization.Work with the team on RC calibration, VCO calibration, IQ calibration, DC offset calibration, DPD, etc.Perform mix signal verification using AMS, Verilog, and system Verilog.Perform RF/analog and digital layout integration.Write test plans, perform design verification, and ATE production support.
Qualification:
Masters or Ph.D. in electrical engineering.Typically requires 5 years of RF/Analog and mixed-signal design experience.Experience in WiFi, BLE, or cellular chip design.Familiar with wireless communication theoryFamiliar with Cadence design tools for simulation and layout.Familiar with EM simulation using EMX/HFSS/ADS.Familiar with Link budget analysis, noise linearity, and phase noise analysis.Familiar with CMOS or SOI on deep submicron or FinFet technology to design circuits.Familiar with chip verification in the lab, using the network analyzer, spectrum analyzer, LitePoint, signal analyzer, etc.Using Verilog, system Verilog, Python, Matlab, and C, etc.Good documentation and communication skills.
Design radio transceiver blocks, such as PA, LNA, mixer, TIA, LPF, VGA, ADC/DAC, etc.Design LO blocks, such as crystal oscillator, RF synthesizer, LO distribution network.Design Analog blocks, such as Bandgap, POR, LDO, DC-DC converter, Low power clock, power detector, ESD, test mux, etc.Guide layout engineer to do the layout, and able to do the critical layout individually with DRC/LVS/xRC.Work with the team to define the block specs, doing link budget analysis, noise, linearity, phase noise, SNR, and EVM optimization.Work with the team on RC calibration, VCO calibration, IQ calibration, DC offset calibration, DPD, etc.Perform mix signal verification using AMS, Verilog, and system Verilog.Perform RF/analog and digital layout integration.Write test plans, perform design verification, and ATE production support.
Qualification:
Masters or Ph.D. in electrical engineering.Typically requires 5 years of RF/Analog and mixed-signal design experience.Experience in WiFi, BLE, or cellular chip design.Familiar with wireless communication theoryFamiliar with Cadence design tools for simulation and layout.Familiar with EM simulation using EMX/HFSS/ADS.Familiar with Link budget analysis, noise linearity, and phase noise analysis.Familiar with CMOS or SOI on deep submicron or FinFet technology to design circuits.Familiar with chip verification in the lab, using the network analyzer, spectrum analyzer, LitePoint, signal analyzer, etc.Using Verilog, system Verilog, Python, Matlab, and C, etc.Good documentation and communication skills.