Power Analysis Engineer

Seeking a talented Front-End- Power Analysis Engineer to join our team. This role focuses on RTL-level power analysis, optimization, and verification to support low-power design initiatives. The ideal candidate will collaborate closely with RTL designers and verification teams to identify power inefficiencies and implement solutions that improve overall design efficiency.

Responsibilities:

• Perform RTL-level power analysis and optimization to support low-power design goals.
• Collaborate with RTL designers and DV teams to identify power hotspots and provide actionable recommendations.
• Develop, enhance, and automate RTL-level power analysis flows, including handling and analyzing large datasets for power modeling.
• Support the implementation of low-power design techniques such as clock gating, power gating, and multiple voltage domains.
• Work closely with verification teams to ensure power-related design changes are correctly validated.

Minimum Qualifications:

• Hands-on experience with RTL design (Verilog/SystemVerilog) and verification methodologies (UVM, assertions, coverage).
• Strong expertise in low-power design and RTL-level power optimization, including UPF usage, power gating, and multiple voltage rails.
• Proven experience with RTL-level power analysis tools such as Power-Artist, PrimeTime PX, or PrimePower.
• Proficiency in scripting for automation (Python, TCL) and familiarity with data analysis/ML frameworks.
• Strong analytical and problem-solving skills with the ability to iterate quickly for optimal results.

Preferred Qualifications:

• Exposure to synthesis flows and RTL-to-GDSII understanding is a plus.
• Experience analyzing IP power characteristics and building power estimation models for software/firmware teams.
• Skills in data modeling and applying machine learning approaches to optimize power at the RTL level.