What are the responsibilities and job description for the Failure Analysis Engineer position at Power Integrations?
Description
Silicon level Failure Analysis Engineer will perform device level failure analysis to support RMA and customer issues.
Responsibilities
The range displayed on the job posting reflects the minimum and maximum target for new hire salaries for this position in California. Within the range, individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training.
Power Integrations also offers to our eligible employees a comprehensive total rewards package that includes equity, medical benefits, ESPP, 401K, tuition reimbursement and time off programs. https://www.power.com/company/our-sustainability-priorities/people-our-engine-innovation.
Silicon level Failure Analysis Engineer will perform device level failure analysis to support RMA and customer issues.
Responsibilities
- Performing fault isolation and defect analysis/characterization on power IC’s to identify root causes of product failures
- Provide comprehensive technical reports to customers on findings from product failure investigations.
- Provide corrective actions to internal and external customers based on the results of the analysis.
- Responsibility will also include effective verbal and written communication of results, which will be used to drive improvements in product design, process technology, and applications. Such communication will require, but not limited to, writing cogent and convincing technical reports suitable for external customers.
- Minimum 2 years of relevant experience
- In-depth understanding of both digital and analog circuits, device physics and IC fabrication processes.
- Ability to interpret IC ATE test data log is required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required. Good technical writing skill is required.
- Hands-on skills in performing electrical fault isolation and defect characterization tools and techniques such as the following: ATE, curve trace, nano/micro-probing, OBIRCH/EMMI microscopy, liquid crystal, CSAM, XRAY, FIB, SEM/EDX and manual cross-sectioning and deprocessing techniques using both parallel-polishing and wet chemical etch techniques.
- Preferences will be given to candidates who have a thorough understanding of analog, mixed-signal, or power semiconductor operational characteristics and the ability to apply fault isolation techniques at chip level as well as PCB at power supply system level.
- BS in Electronic Engineering or equivalent discipline is required; MSEE preferred.
The range displayed on the job posting reflects the minimum and maximum target for new hire salaries for this position in California. Within the range, individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training.
Power Integrations also offers to our eligible employees a comprehensive total rewards package that includes equity, medical benefits, ESPP, 401K, tuition reimbursement and time off programs. https://www.power.com/company/our-sustainability-priorities/people-our-engine-innovation.
Salary : $76,854 - $121,153