What are the responsibilities and job description for the Design Verification Engineer (UVM) position at Nityo Infotech Corporation?
Job Details
Design Verification Engineer (UVM) Contract
Location: El Segundo, CA
Duration: Contract 6 months initially, extendable up to 12 months
Experience: 7 10 years
We are looking for a senior Design Verification Engineer with strong hands-on expertise in UVM-based verification. The ideal candidate has deep experience building and owning verification environments for complex ASIC / SoC designs and is highly proficient with industry-standard verification tools.
Key Requirements
- 7 10 years of ASIC / SoC design verification experience
- Expert-level proficiency in SystemVerilog and UVM methodology
- Proven experience building UVM testbenches from scratch
- Strong background in constrained-random testing, functional coverage, and SVA
- Excellent debugging skills across RTL and testbench environments
- Hands-on expertise with Siemens EDA verification tools (Questa, Veloce preferred)
- Experience with Cadence (Xcelium) or Synopsys (VCS) also acceptable
- Experience verifying standard interfaces/protocols is a plus
Education
- BS or MS in Electrical Engineering, Computer Engineering, or related field
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