What are the responsibilities and job description for the Field-Programmable Gate Arrays Engineer position at netPolarity, Inc. (Saicon Consultants, Inc.)?
Requirement Details:
Job Title: Silicon Desing Engineer (Memory I/O Design Engineer)
Location: Boxborough, MA (100% Onsite)
Contract: 1 Year
Client: AMD
Job Description
We are seeking a Memory I/O Design Engineer to join the High-Speed I/O design team responsible for developing and implementing DDR IPs. This role will primarily focus on SPICE simulations and SystemVerilog behavioral modeling, working closely with an established Analog/Mixed-Signal (AMS) group including the supervisor, AMS manager, IP director, and core design team members.
Top Must-Have Skills
- Circuit simulation & analysis
- SystemVerilog behavioral modeling
- Scripting with TCL, Python, and Shell
Responsibilities
- Run SPICE simulations for circuits such as Transmitters, Receivers (CTLE/DFE), DLLs, DACs, OpAmps, Comparators, and voltage regulators.
- Develop behavioral models of circuit characteristics using SystemVerilog.
- Build tools, write documentation, and define best practices.
- Contribute to developing design flows that improve execution efficiency and quality.
Requirements
- Hands-on experience with HSPICE or Spectre for circuit simulation.
- SystemVerilog behavioral modeling, including Real Number Modeling (RNM).
- Data analysis & scripting using TCL and Python.
- Strong understanding of transistor-level circuit analysis.
- Familiarity with Linux CLI and revision control systems (Perforce preferred).
- Strong communication and documentation skills.
Preferred Skills
- Proven experience in High-Speed I/O circuit design.
- Knowledge of design verification flows.
- Ability to review and understand RTL or firmware code used in custom circuit implementations.
- Experience enhancing tool integrations and writing scripts for automation.
Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering or Computer Engineering.
Salary : $45 - $50