What are the responsibilities and job description for the Principal Memory Design Engineer, HBM position at Micron Technology?
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Principal Design Engineer, you will build the future of memory by architecting and delivering high‑performance DRAM circuit compositions for advanced technology nodes. In this highly visible technical leadership role, you’ll develop innovation across building, layout, verification, and silicon validation. You will collaborate closely with multi-functional teams to deliver scalable, manufacturable solutions for next-generation memory products. Your work will directly influence performance, power, reliability, and time‑to‑market for Micron’s groundbreaking memory technologies
Responsibilities
- Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet aggressive power, performance, and reliability targets
- Develop and refine floorplans, routing strategies, power delivery networks, sense margins, timings, and die‑size tradeoffs
- Perform advanced circuit simulations using FINESIM, HSPICE, and VERILOG, analyzing speed, power, noise, and long‑term reliability
- Model parasitics, verify power and signal integrity, and support validation, reticle experiments, and tape‑out revisions
- Drive simulation‑to‑silicon correlation, identify gaps, and recommend schematic and layout improvements
- Lead technical reviews, documentation, and best‑practice standardization across design and layout teams
- Coordinate and manage layout and build resources, tracking breakthroughs and resolving critical path issues
- Serve as a key technical interface across design, verification, test, and technology development while communicating project status and risks
Minimum Qualifications
- BS in Electrical Engineering or related field, or equivalent experience, with advanced coursework in CMOS circuit building, VLSI, and analog circuits
- Strong hands‑on expertise with Cadence Virtuoso, physical layout, and circuit floorplanning
- Proven experience using FINESIM, HSPICE, and VERILOG for complex circuit simulation and analysis
- Demonstrated ability to solve ambitious technical problems with significant design or innovation impact
- Deep knowledge of DRAM subsystem architecture, operation, or building, with experience leading multi-functional technical efforts
Preferred Qualifications
- MS or PhD in Electrical Engineering or a related field, or equivalent experience
- Strong industry awareness of memory technology trends and emerging design methodologies
- Exceptional communication and leadership skills with the ability to influence across organizations