Senior Mixed-Signal IP Design Engineer

Job Description

MediaTek is a leading global fabless semiconductor company powering more than 2 billion devices a year. Our cutting-edge system-on-chip solutions enable some of the world’s most popular smartphones, smart TVs, connectivity products, IoT devices, and more. We combine deep engineering expertise with a collaborative, fast-paced work environment where innovation, curiosity, and teamwork drive everything we do. About the Role MediaTek is seeking a Senior Mixed-Signal IP Design Engineer with strong architectural modeling and RTL design skills for mixed-signal IP. In this role, you will work closely with analog and digital design teams to build high-level models, evaluate new architectures and features, and develop high-quality SystemVerilog RTL. You will help define and implement state-of-the-art power and performance management solutions for modern CPU, GPU, and NPU products, including clock delivery networks (CDN) and power delivery networks (PDN). Key Responsibilities 1. Understand mixed-signal IP functionality and requirements based on architecture and design specifications. 2. Build high-level architectural models to evaluate new architectures, features, and system-level trade-offs prior to RTL implementation. 3. Analyze model outputs to identify performance bottlenecks and guide architectural decisions and optimizations. 4. Develop high-quality digital designs in SystemVerilog RTL that implement specified computational functions and control sequences. 5. Collaborate with verification teams to support module-level verification and ensure functional correctness. 6. Perform RTL sign-off checks, including LINT, CDC, CLP, and SDC verification. 7. Provide necessary collateral to the physical design team (e.g., SDC, UPF) and work closely with them on performance-critical path analysis and optimization of assigned design blocks.

Main Requirements and Qualifications

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
• 5 years of industry experience in RTL design and/or mixed-signal system development.
• Strong knowledge of digital circuit design, including FSMs, register files, memory subsystems, bus/handshake protocols, and algorithmic logic units.
• Proficiency in SystemVerilog RTL coding, with a solid understanding of synthesis and power, performance, and area (PPA) trade-offs.
• Familiarity with industry-standard EDA tools for RTL simulation, analysis, and quality-check flows.
• Strong communication, presentation, and teamwork skills, with the ability to work effectively in cross-functional environments.
• Scripting skills (e.g., Python, Perl, or similar) are a plus; familiarity with AI-assisted coding tools is also helpful.
• Location: Austin, TX or San Diego, CA
• Salary range: $128,600-$203,600 (depends on the location)
• Employee may be eligible for performance bonus, short- and long-term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.
• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.