What are the responsibilities and job description for the Mixed-Signal IP DFT Engineer position at MediaTek?
Job Description
We are seeking a skilled and motivated Mixed-Signal IP DFT Engineer to join our design team. In this role, you will be responsible for developing and implementing Design for Test (DFT) strategies for mixed-signal IP blocks, ensuring high test coverage and manufacturability. You will work closely with analog, digital, and verification engineers to deliver robust and testable mixed-signal IP solutions. Key Responsibilities:
We are seeking a skilled and motivated Mixed-Signal IP DFT Engineer to join our design team. In this role, you will be responsible for developing and implementing Design for Test (DFT) strategies for mixed-signal IP blocks, ensuring high test coverage and manufacturability. You will work closely with analog, digital, and verification engineers to deliver robust and testable mixed-signal IP solutions. Key Responsibilities:
- Develop and implement DFT architectures and methodologies for mixed-signal IP blocks, including scan insertion and test point insertion for digital portions, and test enablement for analog circuits.
- Collaborate with analog and digital design teams to ensure DFT requirements are incorporated during IP development.
- Perform DFT verification, including ATPG (Automatic Test Pattern Generation), fault simulation, and coverage analysis for digital logic.
- Work with Integration DFT teams to integrate IP-level DFT features into larger systems.
- Document DFT design, verification, and test procedures for mixed-signal IPs.
- Stay current with industry trends and best practices in mixed-signal DFT and testability.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 2 years of experience in DFT implementation for mixed-signal or digital IP blocks.
- Solid understanding of DFT concepts: scan, JTAG, test point insertion and scan diagnosis.
- Experience with DFT/Simulation tools (e.g., Synopsys DFT Compiler, TetraMax/Tessent, VCS, Verdi).
- Familiarity with RTL design (Verilog/VHDL) and simulation; understanding of analog design and test concepts.
- Experience with ATPG, fault grading, and coverage analysis for digital logic.
- Good problem-solving and communication skills.
- Experience with silicon debug and production test is a plus.
- Preferred Skills:
- Experience with scripting languages (Perl, Python, Tcl).
- Knowledge of sub-system integration and hierarchical DFT.
- Familiarity with low-power and mixed-signal design and test challenges.
- Experience working in a multi-site, cross-functional team environment.