Performance IP Design Verification Lead

Job Description

The IP Design Verification Team Lead is responsible for managing and guiding a team of engineers to ensure the functional verification of complex digital IP blocks for Flagship Smartphone/Compute SOCs. This role combines technical expertise with leadership skills to deliver bug-free products. Key Responsibilities

• Leadership & Team Management: Build, mentor, and manage a team of design verification engineers. Assign tasks, drive progress to milestone completion, and ensure team development.
• System Architecture Impact: Collaborate with IP integrators to understand their HW/SW requirements and create the corresponding system checkers
• Verification Planning: Define and own verification methodologies, including constrained-random environments using SystemVerilog/UVM and formal verification
• Execution & Debugging: Create and review team’s test plans, write directed/random test cases, debug failures, and close functional and code coverage.
• Collaboration: Work closely with design teams to scrutinize and ensure all details are added to the specifications, work together to define and ensure full verification coverage.
• Technical Expertise: Implement verification techniques like formal verification, assertion-based methods
• Reporting: Maintain dashboard and drive reviews and process improvements
  
  

Main Requirements and Qualifications

• Master’s degree in Electrical/Computer Engineering or related field.
• 10 years of experience in design verification; 3 years in a leadership role.
• Expertise in SystemVerilog/UVM and formal verification techniques.
• Strong problem-solving skills and debugging skills of RTL/Gate/UPF simulations
• Plus
• Mixed Signal Verification with AMS: define strategy and hands-on experience in bringup and debug