What are the responsibilities and job description for the SERDES SIGNAL INTEGRITY position at Jobs via Dice?
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What You Can Expect
Seeking a Senior Principal SERDES Signal Integrity Engineer to lead SERDES IP validation for next-generation high-performance compute and storage solutions. This role is critical in shaping leadership in Ethernet IEEE 802.3dj and PCIe Gen6 technologies—interfaces that define the future of hyperscale data centers and AI infrastructure.
The ideal candidate will have expertise in signal integrity, board-level design, SERDES architecture, and measurement methods—especially for Ethernet and PCIe interfaces. This position requires a strong background in SERDES IP characterization and design, ideally within the processor industry. The candidate should have deep knowledge of test instrumentation and a strong commitment to ensuring robust characterization for high-volume production.
You will drive electrical characterization and compliance for cutting-edge SERDES IP supporting flagship products. This includes ensuring performance at 112G/224G Ethernet and PCIe Gen6 speeds, enabling ultra-high bandwidth and low-latency interconnects for next-generation compute platforms.
Key Responsibilities:
What You Can Expect
Seeking a Senior Principal SERDES Signal Integrity Engineer to lead SERDES IP validation for next-generation high-performance compute and storage solutions. This role is critical in shaping leadership in Ethernet IEEE 802.3dj and PCIe Gen6 technologies—interfaces that define the future of hyperscale data centers and AI infrastructure.
The ideal candidate will have expertise in signal integrity, board-level design, SERDES architecture, and measurement methods—especially for Ethernet and PCIe interfaces. This position requires a strong background in SERDES IP characterization and design, ideally within the processor industry. The candidate should have deep knowledge of test instrumentation and a strong commitment to ensuring robust characterization for high-volume production.
You will drive electrical characterization and compliance for cutting-edge SERDES IP supporting flagship products. This includes ensuring performance at 112G/224G Ethernet and PCIe Gen6 speeds, enabling ultra-high bandwidth and low-latency interconnects for next-generation compute platforms.
Key Responsibilities:
- Lead electrical characterization and compliance for SERDES IP targeting Ethernet IEEE 802.3dj and PCIe Gen6 standards
- Develop and implement automated validation methodologies, regression frameworks, and compliance test plans
- Drive signal integrity analysis and optimization for high-speed channels, including correlation between simulation and lab measurements
- Provide technical leadership and applications engineering support to strategic customers
- Define CAPEX plans for advanced test equipment and ensure readiness for future SERDES IP development
- Mentor and grow team expertise in high-speed signal integrity and debugging
- Represent the organization in standards committees (IEEE 802.3, PCI-SIG) and contribute to next-generation specifications
- Collaborate on high-speed board design, extraction, and characterization, and partner with internal tools teams to build robust test infrastructure
- Work closely with executive leadership to define long-term SERDES validation strategies
- Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 12 years of experience, OR Master’s/PhD with 7 years
- 5–7 years of direct experience in SERDES characterization and design
- Deep expertise in Ethernet IEEE 802.3ck/dj electrical compliance and validation
- Strong understanding of signal integrity principles, channel modeling, and board-level design for high-speed interfaces
- Hands-on experience with SERDES characterization equipment (oscilloscope, BERT, network analyzer, etc.)
- Experience with scripting languages (e.g., Python)
- Strong problem-solving mindset with ownership of results
- Excellent verbal and written communication skills