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We are looking for a Senior ASIC DFT CDC Constraints Engineer - Remote / Telecommute for our client in Milpitas , CA
Job Title: Senior ASIC DFT CDC Constraints Engineer - Remote / Telecommute
Job Location: Milpitas , CA
Job Type: Contract
Job Overview:
Pay Range: $95hr - $100hr
Requirement/Must Have:
We are looking for a Senior ASIC DFT CDC Constraints Engineer - Remote / Telecommute for our client in Milpitas , CA
Job Title: Senior ASIC DFT CDC Constraints Engineer - Remote / Telecommute
Job Location: Milpitas , CA
Job Type: Contract
Job Overview:
Pay Range: $95hr - $100hr
Requirement/Must Have:
- 10 years of ASIC/SoC experience with 5 years in SDC constraint development and STA sign-off.
- Strong expertise in CDC synchronization structures and SDC constraint representation.
- Hands-on experience with PrimeTime, Tempus, or Fusion Compiler.
- Experience with SpyGlass CDC or JasperGold CDC for structural CDC analysis.
- Strong understanding of metastability, MTBF, and synchronizer settling time budgets.
- Experience constraining Gray-code FIFO pointers and pulse synchronizers.
- Solid understanding of scan insertion, scan chain stitching, and ATPG flow.
- Experience authoring DFT-mode SDC views including shift, capture, and at-speed modes.
- Familiarity with Tessent or Synopsys DFTC ATPG toolchain.
- Ability to debug X-propagation issues in scan mode arising from unconstrained CDC paths.
- 10 years of experience in ASIC/SoC development.
- 5 years of hands-on experience in SDC constraint engineering and STA sign-off.
- Extensive experience in CDC theory, ATPG methodology, and timing closure.
- Own and develop SDC/SSTA constraint strategies for functional and DFT scan-mode operations.
- Work on CDC violations impacting scan-shift failures and at-speed test escapes.
- Perform timing analysis and sign-off activities using industry-standard STA tools.
- Develop and maintain DFT-mode timing constraints for scan shift and capture operations.
- Analyze and resolve metastability and synchronization issues across clock domains.
- Debug and resolve scan-mode X-propagation issues.
- Collaborate with DFT, STA, and design teams for timing closure and test coverage improvements.
- Strong analytical and debugging skills.
- Ability to work in highly complex multi-clock SoC environments.
- Excellent understanding of CDC methodologies and DFT architectures.
- PrimeTime
- Tempus
- Fusion Compiler
- SpyGlass CDC
- JasperGold CDC
- Tessent
- Synopsys DFTC
- ATPG
- STA
- CDC Analysis
- SDC Constraints
- ASIC/SoC Design
- Bachelor s or Master s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related technical field.
Salary : $95 - $100