Need Physical Design Engineer in Cupertino CA

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Hi,

Role: Physical Design Engineer

Location: Cupertino, CA

Duration: Long Term

Work mode: 5 Days Onsite

Visa Type: Any visa

• Experience:* 5 15 Years
  
  

Key Responsibilities

• Execute end-to-end physical design implementation including:
• Floorplanning
• Power grid design
• Placement & Routing
• Clock Tree Synthesis (CTS)
• Timing Closure
• Signal/Power Integrity Signoff
• Physical Verification (DRC/LVS/Antenna)
• EM/IR Analysis
• DFM Closure
• Perform full-chip and block-level timing analysis and provide optimization guidance to subsystem/block owners.
• Work on advanced low-power and high-performance SoC designs.
• Drive design convergence and signoff closure across multiple implementation stages.
• Collaborate with cross-functional teams including RTL, STA, DFT, and Signoff.
  
  

Required Skills

• Strong hands-on experience with Cadence and Synopsys EDA tool suites.
• Expertise in STA and timing signoff using Synopsys PrimeTime.
• Experience handling large block/subsystem/full-chip implementation.
• Strong scripting knowledge in TCL, Perl, Shell, and Make flows.
• Good understanding of advanced technology nodes including 7nm/5nm/3nm.
• Strong debugging, analytical, and communication skills.
• Self-driven and capable of driving new methodologies and automation.
  
  

Qualifications

Bachelor's or Master's degree in Electronics / VLSI / Electrical Engineering.