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Detailed Job Description:
Title:
Design Verification Engineer/Engineer, Staff|6155
Location:
San Diego California 92121
Duration:
12 months (Possible Extension)
Pay rate:
$65-$81/Hr on W2 without PTO
Work authorization:
, , EAD
Shift:
1st
Job Description
Top 5 Required Skills
Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.,
Keywords
USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL,
General Summary:
Join design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.
Responsibilities:
Required Years Of Experience
5 years ASIC design verification, or related work experience.
Comments for Suppliers
Detailed Job Description:
Title:
Design Verification Engineer/Engineer, Staff|6155
Location:
San Diego California 92121
Duration:
12 months (Possible Extension)
Pay rate:
$65-$81/Hr on W2 without PTO
Work authorization:
, , EAD
Shift:
1st
Job Description
Top 5 Required Skills
- Knowledge of a HVL methodology like SystemVerilog/UVM.
- Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.
- Protocol knowledge of High Speed Serdes external interfaces like PCIe, USB3/4, UFS, MIPI CSI/DSI/HDMI and DDR PHY
- Would be plus if candidate has working exp on UPF based power aware simulations and Gate level simulations
- Good at implementing system Verilog assertions and checkers, good debugging skills
Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.,
Keywords
USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL,
General Summary:
Join design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.
Responsibilities:
- Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.
- Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality.
- Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
- Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.
- From scratch VIP development experience for Serdes controller PHY is an additional plus
- Experience with Low power design verification, Formal verification and Gate level simulation.
- Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.,
- Experience in scripting languages (Python, or Perl).
- Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.
Required Years Of Experience
5 years ASIC design verification, or related work experience.
Comments for Suppliers
- Rounds of interviews to be expected: 1-2 Interview Method: Video conference Work Location Requirement 100% onsite Work Address: 5745 Pacific Center Blvd, San Diego, CA 92121 Workdays: Mon-Fri Shift Time: 830-5:00pm PST Weekly / Daily Expected Hours: 40.0 / 8.0
Salary : $65 - $81