What are the responsibilities and job description for the Design Verification Engineer position at ACL Digital?
Top 5 Required Skills
- HVL Methodology: SystemVerilog/UVM.
- Simulation/Formal Tools: VCS, Xcellium/NCsim, Questa, VCFormal, Jaspergold.
- Protocols: High-speed Serdes interfaces (PCIe, USB3/4, UFS, MIPI CSI/DSI/HDMI, DDR PHY).
- Advanced Simulations (Plus): UPF-based power-aware simulations & Gate Level Simulations (GLS).
- Assertions/Debug: SystemVerilog Assertions (SVA), checkers, strong debugging.
Technologies
- Protocols: PCIe, USB, MIPI, LPDDR, CXL, C2C, D2D, UFS.
- Analog Blocks: PLL, DAC, ADC, Sensors.
Minimum Qualifications
- Education: Master’s or Bachelor’s in EE, CE, or related.
- Experience: 5 years in ASIC design verification or related.
Pay Rate: $70/hr - $80/hr
Salary : $70 - $80