DFT engineer

Hiring: DFT / ATPG Engineer

Location - Santa Clara

We are looking for an experienced DFT / ATPG Engineer to join a high-performance semiconductor design team working on advanced SoC/ASIC technologies. The ideal candidate will have strong expertise in scan insertion, ATPG, MBIST, IJTAG, and DFT verification methodologies.

Key Responsibilities

• Implement DFT architectures including SCAN, SSN, MBIST, and Boundary Scan
• Perform ATPG pattern generation, debug, and coverage analysis
• Execute DFT insertion and verification using industry-standard EDA tools
• Develop and verify MBIST architectures and repair implementations
• Support clock DFT verification and high-speed IO testing
• Debug DRC violations and ATPG/scan issues
• Generate collaterals for Test Timing and Physical Design teams
• Verify DFT features including JTAG, Boundary Scan, SCAN, MBIST, ATPG, and High-Speed IO
• Collaborate with RTL, Verification, and Physical Design teams across the development cycle

Required Qualifications

• BE/B.Tech in Electronics, Electrical Engineering, or related field
• 5 years of hands-on DFT and ATPG experience in SoC/ASIC development
• Strong understanding of:
• Scan-based testing
• Controllability & Observability
• Digital Design & RTL fundamentals
• Clock DFT concepts
• Experience with:
• ATPG pattern generation and debug
• MBIST insertion and repair verification
• IJTAG IEEE 1687 standards
• ICL and PDL specifications
• High-Speed IO testing
• Familiarity with Siemens Tessent or equivalent DFT tool suites
• Strong analytical, debugging, and communication skills

Preferred Skills

• Siemens Tessent
• Synopsys DFT Compiler
• Cadence Modus
• Verilog/SystemVerilog
• TCL/Perl/Python scripting
• Linux/Unix environment

Keywords

#DFT #ATPG #MBIST #ASIC #SoC #Semiconductor #RTL #JTAG #BoundaryScan #Tessent #VLSI #EngineeringJobs #Hiring #ScanInsertion #IJTAG #Verification