What are the responsibilities and job description for the Technology Development Quality and Reliability Engineer position at Intel?
Job Details
Job Description:
The successful candidate will be working in Technology Development ESD, LU reliability engineering group focusing on research and development in Electrostatic Discharge (ESD) and Latch-up reliability area. This position is responsible for developing solutions and design rules to ensure ESD and latch-up reliability in circuits. The engineer will be responsible for but not limited to design test structures, run experiments, analyze data from test structures during technology development phase. ESD characterization on test structures using transmission line pulse (TLP) is required. Responsibilities also include develop, document, and publish design rules to aid internal and foundry design teams. Serve as a consultant to design teams to ensure ESD risks are addressed in analog circuits.
Qualifications
Minimum Qualifications:
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $155,520.00 - 219,550.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Description:
The successful candidate will be working in Technology Development ESD, LU reliability engineering group focusing on research and development in Electrostatic Discharge (ESD) and Latch-up reliability area. This position is responsible for developing solutions and design rules to ensure ESD and latch-up reliability in circuits. The engineer will be responsible for but not limited to design test structures, run experiments, analyze data from test structures during technology development phase. ESD characterization on test structures using transmission line pulse (TLP) is required. Responsibilities also include develop, document, and publish design rules to aid internal and foundry design teams. Serve as a consultant to design teams to ensure ESD risks are addressed in analog circuits.
Qualifications
Minimum Qualifications:
- Master's degree in Electrical Engineering, Reliability Engineering, Physics, or related technical field.
- 3 years experiences in ESD or LU reliability engineering
- 3 years of experience with Device Physics, device characterization and/or basic VLSI design knowledge
- Ph.D. in electrical engineering and 1 years of experience in ESD, LU reliability engineering
- Experience in planning and guiding the creation of test structure layout on test chips.
- Experience in VLSI circuit design, including analog and digital. Knowledge of state-of-the-art ESD circuit design techniques and topologies.
- Deep understanding of transistor device characteristics and characterization methods.
- Experience with transmission line pulse (TLP) measurement. Experience on ESD models (i.e. CDM, HBM)
- Data analysis background (JMP, Excel) to support design of experiments and analysis.
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $155,520.00 - 219,550.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Salary : $155,520 - $219,550