Senior Design Verification Engineer

Job Title: Sr. Staff Design Verification Engineer

Location: Boise, ID

Duration: Perm

Schedule: On-site 5 days a week

Pay: $140,000-180,000

Requirements:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5 years of professional experience in ASIC/SoC verification, OR Master's degree and/or PhD with 3 years of experience
• Strong background in SoC verification and UVM-based testbench development using SystemVerilog, with proven experience architecting and implementing constrained-random verification environments
• Deep understanding of verification methodology including object-oriented programming, coverage-driven verification closure, directed and randomized testing strategies, and assertion-based verification
• Hands-on experience with industry-standard simulation tools including Synopsys VCS, Cadence Incisive/Xcelium, or Mentor Questa for RTL and gate-level verification
• Strong scripting skills in Python, Perl, Tcl, or shell scripting for test automation, regression management, coverage analysis, and verification flow development
• Experience with the full verification lifecycle from test plan development through coverage closure, working across multiple verification platforms (simulation, emulation, post-silicon)
• Solid understanding of modern SoC architectures, industry-standard interfaces and protocols including AXI, AHB, PCIe, CXL, DDR/LPDDR, and high-speed SerDes

Plusses:

• Experience with formal verification tools and methodologies including connectivity checking, property verification, and equivalence checking
• Hands-on experience developing verification infrastructure for custom silicon, AI accelerators, or high-performance compute platforms
• Familiarity with advanced verification techniques including emulation/FPGA prototyping, hardware-software co-verification, and post-silicon validation support
• Knowledge of low-power verification methodologies including UPF (Unified Power Format) and power-aware simulation techniques
• Proficiency in C/C programming for verification infrastructure development, reference model creation, and integration with DPI-based testbench components
• Background in high-speed interface verification including 112G SerDes, PCIe Gen 6/7, CXL 3.0, or custom die-to-die interconnects
• Experience with memory subsystem verification including HBM, DDR/LPDDR controllers, or custom memory architectures
• Familiarity with verification metrics tracking, regression management systems, and continuous integration flows for large-scale SoC projects
• Experience mentoring junior verification engineers and contributing to verification methodology development
• Participation in customer-facing technical discussions and design reviews for custom ASIC development