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AMD Versal / PL Integration & IPC Engineer (iRDK)

Info Way Solutions
Palo Alto, CA Contractor
POSTED ON 7/29/2026
AVAILABLE BEFORE 8/27/2026

Job Title: AMD Versal / PL Integration & IPC Engineer (iRDK)

Location: Palo Alto, CA (Preferred)

Work Authorization: U.S. Citizen (USC) or Green Card Holder (GC)

Job Summary

We are seeking an experienced AMD Versal / PL Integration & IPC Engineer to drive AMD Versal SoC bring-up for the iRDK platform, with a focus on programmable logic (PL) integration and inter-processor communication (IPC) with the AMD APU. The ideal candidate will have hands-on experience with Versal or Zynq UltraScale platforms, FPGA integration, embedded software development, and real-time system validation.

Responsibilities

  • Bring up AMD Versal SoC on iRDK custom board from EVK reference.
  • Develop and validate PL integration, including IP instantiation, configuration, and AXI interfaces.
  • Implement and validate IPC mechanisms between Versal AI Core / RPU and AMD APU using RPMsg, OpenAMP, and shared memory.
  • Develop BSP and drivers for Versal PS subsystems (RPU and APU partitions).
  • Work with AMD/Xilinx platform tools, including Vitis and Petalinux.
  • Validate real-time latency and data throughput across the PL–PS–APU boundary.
  • Bring up sample applications on PL IP Integration and Versal/X86 interfaces.

Qualifications

  • Bachelor's or Master's degree in Computer Science, Engineering, or a related field.
  • 5 years of experience in Embedded Software Development.
  • Hands-on experience with Versal or Zynq UltraScale bring-up.
  • Experience with FPGA/PL driver integration, including Vitis HLS, IP integration, and AXI interconnect.
  • Experience implementing IPC using RPMsg, OpenAMP, or shared-memory communication.
  • Experience with Petalinux / Yocto and Xilinx/AMD SDK toolchain.
  • Strong programming skills in C/C , Python, or Rust.
  • Experience with hardware debugging and Xilinx debug tools.

Preferred Skills

  • Hands-on experience with AMD Versal AI Core or Versal Premium.
  • Experience in the Automotive domain (ADAS or Cockpit).
  • Experience with safety-capable RPU lockstep configuration.
  • Experience with DMA engines and high-bandwidth PL–PS data paths.

Required Skills

  • AMD Versal SoC
  • Programmable Logic (PL)
  • Inter-Processor Communication (IPC)
  • AMD APU
  • RPMsg
  • OpenAMP
  • Shared Memory
  • Embedded Linux
  • BSP Development
  • Device Driver Development
  • Vitis
  • Petalinux
  • Zynq UltraScale
  • AXI Interconnect
  • FPGA Integration
  • C/C
  • Python
  • Rust
  • Hardware Debugging
  • Xilinx Toolchain

Hourly Wage Estimation for AMD Versal / PL Integration & IPC Engineer (iRDK) in Palo Alto, CA
$56.00 to $65.00
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