Field-Programmable Gate Arrays Engineer

Job Title: Sr Electrical Engineer - FPGA & ASIC Design Solutions

Location: Cedar Rapids, IA

Rate: $100- $113/hr on W2

Duration: 12 months

Job Description:

Sr Electrical Engineer - FPGA & ASIC Design Solutions

Become part of the growing FPGA & ASIC Design Solutions team. As an engineer in this organization, you will be a member of an experienced, dynamic design group employing best practice design methodologies supporting our next generation of military GPS products.

This position is for an experienced and motivated Senior Electrical or Computer engineering candidate to be involved in the design, implementation, verification and integration of military GPS products.

Key Responsibilities will include:

Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration

RTL coding and simulation in VHDL or Verilog

Testbench development for the verification of RTL blocks using VHDL or SystemVerilog

This position requires these skills and abilities:

RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using UVM and SystemVerilog

Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure

Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synopsys, FPGA-specific tools)

Familiarity with revision control concepts and tools (e.g. Subversion)

Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds

Strong oral and written communication skills and the ability to document and present one's work and status

Bachelor's Degree in applicable engineering field

Desired skills of a successful candidate:

Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)

ASIC / FPGA lab validation with advanced lab equipment

Design for Test (DFT) and manufacturability issues

Experience with Unix, scripting, C/C , and/or Perl