Sr Design for Test Engineer

At-a-Glance:

Are you ready to build your career by joining a leading global provider of product engineering and semiconductor design services? If so, our client is hiring a Sr Design for Test Engineer.

Position Type:

• Contract
• Remote
  
  
  

Required:

• 5 - 7 years of experience in DFT.
• Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing).
• MBIST Insertion and Verification.
• Experience in IEEE 1149.1 JTAG Insertion and verification.
• Scripting languages like Perl, Shell, and TCL.
• Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes.
• Tools: Mentor Tessent.
• B. Tech, M.Tech in Microelectronics/Electronics
• Excellent communicator.
• Low power DFT.
  
  
  

Responsibilities:

• DFT implementation for 3nm and 5nm Networking chips, IP DFT work.
• RTL checks for scan-insertion compatibility using Synopsys Spyglass.
• Scan-Insertion using Tessent TestKompress.
• ATPG pattern generation:
• Compressed and Uncompressed Mode.
• Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax
• Pattern Simulation:
• Without timing, with timing for different corners.
• Tools: VCS.
• Mismatch debug using Verdi.
• Scripting with Perl, Shell, TCL:
• DAeRT - DFT flow enhancement/automation in project.
• Makefile enhancement using extended scripts and targets for flow enhancement.
• MBIST Insertion and Verification:
• MBIST Insertion and Verification done on block on top.
• Silicon debug and bring-up done for block and top.
• IEEE 1149.1 JTAG Insertion and verification.
  
  
  

Get in Touch:

We want to hear from you! If you think you'd be a good match, submit your resume and reach out to Priyanshu at 201-478-6913 to learn more.

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