CAD Engineer

Job Description:

Seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the

high speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow

including PDK installation and support, tool support and installation, layout support, design

support including schematic and simulation, design archive and tapeout.

The engineer must be an expert in analog and mixed-signal circuit design flows and tools.

Tasks will include significant tool and PDK customization including SKILL and PCELL coding as

well as design team support. The self-motivated engineer must be able to anticipate problems

and devise effective solutions.

Responsibilities:

 Install, customize and support external vendor PDK’s for both SiGe and CMOS processes

 Install, customize and support Custom IC and RF CAD tools for the design of high-speed

(10–40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline

applications.

 Execute and support layout efforts including DRC/LVS user support and archive and

tapeout processes

Minimum Expertise Requirements:

 Expert in high-speed analog and mixed-signal IC design concepts and must demonstrate

superior critical thinking skills, problem solving capabilities and engineering judgment.

 Fluent with analog EDA front and back-end tools

 Cadence Virtuoso, ADE

 Strong SKILL programming a MUST

 Mentor Calibre (end user support and rule deck writing)

 Detailed understanding of advanced high-speed analog & mixed-signal layout concepts

 FlexLM license management

 Strong UNIX/Linux knowledge

 Not required but preferred

 Ocean scripting and advanced modelling and simulation knowledge

 Linux OS support

Minimum Experience Requirements:

 5 years of experience working as a high-speed analog & mixed signal IC CAD professional

is required

 IC Technologies: High-speed IC technologies, including CMOS and bipolar.

 IC Design Software:

 Experience with configuring, documenting, and maintaining high speed analog IC design

flows is a must.

 Experience with transistor-level IC design and verification software, e.g. Cadence

Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill

language, is a must.

 General understanding of digital physical design flows, e.g. RTL coding, place and

route, DRC/LVS verification.

 Work Environment: Comfortable working in a fast-paced environment. Must be strong

individual contributor, and also able to work as member of a small team. Must be able

to support EPDA users and solve problems efficiently, effectively and rapidly.

Education Requirements:

 BS 5 years

 MS 4 years

 PhD 3 years