Lead RFIC ASIC Design Engineer

Title: Lead RFIC ASIC Design Engineer

Duration: Permanent / Full-time

Location: Hillsboro, OR (Hybrid: onsite 3 days per week)

Salary Range: $160,000 to $225,000 per year

**Candidates must have valid U.S. work authorization at the time of hire. Visa support available via H1 transfer only **

Our client, a leader in the test-and-measurement and wireless communications industries, is seeking passionate individuals with a vision for the future, a desire to impact the world, and a drive to bring innovative ideas to life. They are building development teams to create the next generation of RFICs and ASICs for advanced communication systems. The team is currently seeking a skilled and motivated Lead RFIC ASIC Design Engineer to drive the development of cutting-edge RF and analog circuits for applications in wireless communications and beyond. This is an exciting opportunity to contribute to high-impact projects that will shape the future of communication technologies.

Position Description:

The role involves leading a design team to create both full chips and large analog macros. Responsibility includes thinking at the higher chip level, performing block aggregation, and making decisions on trade-offs between various block partitioning schemes. Close collaboration with layout engineers on top-level floor-planning is required to ensure optimized designs.

With a thorough understanding of analog circuit design, independent design of various functional blocks will be expected, along with in-depth knowledge of BiCMOS and CMOS process technologies. Expertise in simulation models, design rules, and verification procedures (DRC/LVS/ERC) will be applied, while also focusing on minimizing device mismatch, noise, signal coupling, and ESD.

The role entails designing analog integrated circuits for complex mixed-signal SoCs, taking them from creation through to production. Collaboration with cross-functional teams will be essential to meet design objectives and schedules.

Position Responsibilities:

• Manage large analog block / full-chip schematics to ensure correct connectivity and functionality.
• Assist layout floor-planning efforts at a high-level.
• Design and implement high speed analog/mixed-signal circuits in advanced CMOS/BiCMOS technology for integration in high performance mixed-signal SoCs.
• Clearly communicate with team members the various requirements or design conflicts.
• Design, simulate, analyze, model, document and communicate integrated circuit IP.
• Understand system level design requirements as applied to integrated circuit design.
• Characterization and debugging of analog IC designs for testing and measurement equipment.

Position Qualifications:

• M.S. in Electrical Engineering.
• 5 – 10 years of work experience in IC Design.
• Proven ability to technically lead a design team to create both full chips and large analog macros.
• Thinks at the higher chip level to do block aggregation.
• Understands trade-offs between various block partitioning schemes.
• Experience doing top-level floor-planning with a layout engineer.
• Thorough understanding of detailed analog circuit design and the ability to design independently various functional blocks.
• In-depth understanding of BiCMOS and CMOS process technologies
• Understanding of simulation models, design rules and verification procedures (DRC/LVS/ERC)
• Experience with design practices such as minimizing device mismatch, noise, signal coupling, ESD
• Experience designing analog integrated circuits for a complex mixed signal SoCs from creation into production.

Our client offers the following benefits for this position: medical, dental, & vision insurance, short-term and long-term disability, life and AD&D insurance, 401(k) retirement plan, paid holidays and vacation and much more.