What are the responsibilities and job description for the Post-Silicon Validation Engineer position at Etched?
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Job Summary
We are seeking a highly skilled and motivated Post Silicon Validation Engineer to join our dynamic team. The ideal candidate will be responsible for bringing up, validating, and characterizing complex SoCs from first silicon through the production ramp. This role is crucial in ensuring functional correctness, performance, and reliability of our AI/ML accelerator hardware, enabling successful deployment of our cutting-edge products.
Key Responsibilities
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Job Summary
We are seeking a highly skilled and motivated Post Silicon Validation Engineer to join our dynamic team. The ideal candidate will be responsible for bringing up, validating, and characterizing complex SoCs from first silicon through the production ramp. This role is crucial in ensuring functional correctness, performance, and reliability of our AI/ML accelerator hardware, enabling successful deployment of our cutting-edge products.
Key Responsibilities
- Lead early silicon bring-up, including boot, initialization, and system-level debug.
- Diagnose complex silicon issues across RTL, firmware, and hardware layers.
- Collaborate with design, verification, and board teams to root-cause and resolve issues.
- Validate and characterize custom IP blocks and accelerator components.
- Execute performance validation, stress testing, and corner-case analysis for compute units.
- Develop and maintain post-silicon validation infrastructure, automation, and regression frameworks.
- Use lab instrumentation (oscilloscopes, analyzers, BERTs, pattern generators) for detailed signal and system characterization.
- Define validation strategies, coverage metrics, and signoff criteria across subsystems.
- Work cross-functionally with RTL, DFT, ATE, firmware, and architecture teams to ensure smooth pre- to post-silicon transitions.
- Provide feedback on test escapes, yield issues, and errata to guide silicon revisions and firmware updates.
- 7–12 years of experience in post-silicon validation, bring-up, and debug of complex SoCs.
- Proven expertise in early silicon bring-up, debug, and system-level validation.
- Deep understanding of board-level interfaces and peripheral protocols.
- Proficiency in C, Python, and scripting for validation automation.
- Hands-on experience with lab tools such as oscilloscopes, logic analyzers, and protocol analyzers.
- Familiarity with firmware, bootloaders, and low-level silicon debug environments.
- Strong analytical, problem-solving, and collaboration skills across hardware and software disciplines.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred).
- {Low-speed peripheral interfaces (I2C, SPI, UART, JTAG).
- High-speed protocols such as PCIe or Ethernet.
- Memory subsystems (HBM, DDR).
- Performance and thermal characterization.
- AI/ML model profiling and workload correlation.
- System-level validation of AI accelerators or server-class platforms.
- $200,000 - $275,000
- Full medical, dental, and vision packages, with generous premium coverage
- Housing subsidy of $2,000/month for those living within walking distance of the office
- Daily lunch and dinner in our office
- Relocation support for those moving to San Jose (Santana Row)
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Salary : $200,000 - $275,000