What are the responsibilities and job description for the DFT Intern position at Etched?
About Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment.
You may be a good fit if you have
Program details
How We’re Different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment.
You may be a good fit if you have
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with a hardware description language (Verilog or SystemVerilog)
- Exposure to ASIC or SoC design concepts
- Familiarity with digital logic design fundamentals
- Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
- Familiarity with scripting in Python, Tcl, or another language
- Are able to learn quickly about transformers and other aspects of modern artificial intelligence
- Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
- Experience with Tessent or similar DFT tooling
- Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
- Exposure to DFT flow automation or regression infrastructure
- Familiarity with clocking and reset schemes
Program details
- 12-week paid internship (June - August 2026)
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Based at our office in San Jose, CA
- Direct mentorship from industry leaders and world-class engineers
- Opportunity to work on one of the most important problems of our time
How We’re Different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.