What are the responsibilities and job description for the Senior Design Verification Engineer position at Econosoft?
We are seeking a Senior Design Verification Engineer with strong SystemVerilog and UVM expertise to support verification of high-performance power distribution systems. The role involves developing UVM testbenches, validating designs, debugging issues, and driving verification closure in a fast-paced hardware environment.
Must Have Skills:
• 8 years of Design Verification experience
• Strong SystemVerilog and UVM production experience
• Built and deployed at least 5 UVM testbenches in production
• Experience achieving full code coverage and verification closure
• Background validating power distribution systems with p99 latency targets under 10ms.
Good to Have Skills:
• DSP verification experience
• Familiarity with 5G standards and protocols.
Tech Environment:
• SystemVerilog
• UVM
• High-performance power distribution systems