Demo

Design Engineer

Creospan Inc.
Sunnyvale, CA Contractor
POSTED ON 4/14/2026
AVAILABLE BEFORE 5/13/2026

Job Title: Design Engineer – ASIC Power Engineer

Location: Sunnyvale, CA (Hybrid)

🔧 Key Responsibilities:

  • Perform RTL and netlist-level power analysis & optimization
  • Support PPA optimization using Fusion Compiler
  • Analyze and debug reports from Synthesis, PD, Timing, and Power flows
  • Implement low-power methodologies and UPF
  • Develop automation scripts for report and data analysis

✅ Required Skills:

  • 2 to 10 years experience in ASIC Power / Low-Power Design
  • Hands-on experience with PrimePower / PTPX or Cadence Joules
  • Experience with DC, ICC, VCS, Verdi
  • Strong scripting skills in Python / Perl / Tcl
  • Experience working with UPF and power estimation flows

⭐ Nice to Have:

  • Silicon power characterization experience
  • IP / SoC-level power profiling exposure
  • Data visualization using Excel / MATLAB

📩 Please share your updated resume if interested.

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