What are the responsibilities and job description for the Senior Design Verification Engineer position at ComTec Information Systems (IT)?
Position: Digital SoC Design Verification Principal Engineer/Manager
Location: San Jose, CA
Job Requirements:
- Master's and/or Bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS
- At least 15 years of experience in digital SoC verification, with 5 years in a leadership or management role.
- Proven success in leading complex SoC verification projects from concept to mass production, demonstrating strong leadership and technical expertise.
- Hands-on experience in System Verilog, Verilog, mixed-signal SoC simulation, and FPGA-based verification.
- Deep understanding of digital and mixed-signal IP integration, including custom RTL and digital/analog co-verification.
- Familiarity with HW emulators, embedded systems, wireless protocols, and signal processing.
- Proficiency in programming languages such as C, Python, and Tcl for test bench architectures and automation.
- Demonstrated ability to lead, manage, and mentor a dispersed engineering team, fostering a high-performance culture.
- Strong schedule and resource management background, with an ability to prioritize tasks effectively across multiple projects.
- Excellent communication and presentation skills, capable of effectively conveying technical details to both technical and non-technical stakeholders.
Desirable Skills:
- Track record of successfully executing block or chip-level verification plans.
- Deep understanding of the complete verification life cycle (test plan, testbench through coverage closure).
- Knowledge of Cadence verification tools and UVM verification methodologies.
- Experience with wireless communication standards such as 3GPP, WiFi, 4G/5G, or similar technologies.
- Ability to thrive in environments with changing or incomplete requirements while developing creative solutions and workarounds.
