Technical Project Manager (ASIC/SoC Design)

Role Description

This is a full-time, on-site role for a Technical Project Manager (ASIC/SoC Design) located in San Jose, CA. The role involves overseeing and managing the lifecycle of ASIC/SoC design projects, ensuring they are completed on time, within scope, and on budget. As a Technical Project Manager, you will serve as the primary bridge between global fabless customers and internal engineering teams. You will lead complex SoC (System-on-Chip) development programs from initial architecture alignment through Final GDSII delivery (Tape-out) and mass production, ensuring technical milestones, project schedules, and business objectives are successfully achieved. 

1. Key Responsibilities

• Project Lifecycle Management: Lead the end-to-end execution of ASIC design projects, including RTL design, DFT, Synthesis, Physical Design (P&R), and Sign-off (STA, DRC/LVS).

• Stakeholder Management: Act as the main point of contact for tier-1 fabless customers, foundry partners (e.g., Samsung Foundry), and IP vendors (e.g., Arm, Synopsys).

• Schedule & Resource Planning: Develop detailed project timelines and allocate engineering resources across multi-site teams (e.g., Korea, USA, Taiwan) to ensure on-time delivery.

• Risk Mitigation: Proactively identify technical bottlenecks in advanced nodes (2nm/4nm) and implement contingency plans to avoid schedule slips.

• Technical Alignment: Moderate technical discussions regarding power, performance, area (PPA) trade-offs, and advanced packaging requirements (2.5D/3D, HBM, Chiplets).

• Financial Oversight: Manage project budgets, NRE (Non-Recurring Engineering) costs, and invoicing milestones.

2. Qualifications & Requirements

Technical Expertise

• Educational Background: B.S. or M.S. in Electrical Engineering, Computer Science, or a related technical field.

• Industry Experience: 7 years of experience in the semiconductor industry, with a proven track record of managing high-performance SoC projects.

• Design Flow Knowledge: Deep understanding of the RTL-to-GDSII flow, including timing closure, power analysis, and physical verification.

• Advanced Node Experience: Hands-on experience or strong familiarity with FinFET/GAA processes and advanced packaging technologies (UCIe, CoWoS, etc.).

Professional Skills

• Communication: Excellent verbal and written communication skills in English.

• Leadership: Ability to lead cross-functional teams without direct authority and manage conflict in high-pressure environments.

• Tools: Proficiency in project management software (Jira, Confluence, Microsoft Project) and familiarity with EDA tool capabilities.

3. Preferred Qualifications

• Foundry Experience: Previous experience working within a Foundry (Samsung, TSMC) or a major DSP (Design Solution Partner) ecosystem.

• Market Insight: Knowledge of specific high-growth sectors such as AI/HPC, or Automotive.

Benefits

• Medical, Dental, and Vision Coverage

• 401(k) Retirement Plan with Company Matching

• Paid Time Off (PTO) and Company Holidays

• On-site Fitness Center Access

• Collaborative and Global Team Environment

• Career Growth Opportunities within a Global Semiconductor Company