DFT Engineer

Senior DFT Engineer (W2 Full time)

Location: San Jose, CA

Job Type: Full-Time

Experience: 10 years

Education: Bachelor’s or Master’s Degree

About the Role

We are seeking an experienced DFT Engineer to join our ASIC development team in San Jose, CA. The successful candidate will lead DFT activities from chip-level DFT architecture and specification through implementation, verification, silicon bring-up, and production release.

This role involves working across multiple phases of SoC DFT, including DFT architecture, test insertion, ATPG, coverage improvement, post-silicon debug, and yield improvement. You will collaborate closely with Physical Design, STA, Test Engineering, Manufacturing, Reliability, and other cross-functional teams.

Key Responsibilities

• Define DFT specifications based on product requirements, customer requirements, DPPM goals, and test metrics.
• Implement DFT features including Scan, MBIST, TAP, LBIST, IO, SerDes, and other IP-level DFT integration.
• Perform chip-level pattern generation, verification, debugging, and coverage improvement.
• Generate, verify, and debug test vectors prior to tape-out.
• Validate and debug test vectors during silicon bring-up and ATE testing.
• Work closely with STA and Physical Design teams to achieve DFT mode timing closure.
• Support silicon failure analysis, diagnostics, yield improvement, and RMA activities.
• Interface with customer, physical design, test engineering, manufacturing, and reliability teams globally.
• Collaborate with IP DFT engineers and other stakeholders to resolve testability challenges.
• Debug customer-returned parts using ATE.
• Develop innovative DFT solutions for advanced process nodes, including 3nm and beyond.
• Automate DFT and test-vector generation flows.
• Track and prioritize deliverables across multiple cross-functional teams and projects.

Required Qualifications

• Bachelor’s degree with 12 years of related experience, or Master’s degree with 10 years of related experience.
• Strong hands-on DFT experience in areas such as IO/Analog DFT, ATPG, Scan, BIST, and related technologies.
• Experience with scan insertion and scan compression, including tools such as DFT Compiler and Mentor TestKompress.
• Strong experience with Logic BIST (LBIST) design and debug.
• Extensive experience with ATPG vector generation, simulation, and debugging, including TetraMax or FastScan.
• Experience with Verilog coding, testbench development, and simulation.
• Hands-on experience with Memory BIST (MBIST) insertion and verification for SRAM, CAM, eDRAM, ROM, and other embedded memories.
• Experience with Boundary Scan verification and test-vector generation.
• Strong knowledge of IEEE 1149.1 and IEEE 1149.6.
• Knowledge of Test-STA and timing constraints.
• Strong understanding of IEEE 1687, IJTAG, ICL, and PDL.
• Strong understanding of digital and analog circuit design fundamentals and device physics.
• Knowledge of silicon processing, logical and physical synthesis, and transistor reliability principles.
• Excellent debugging, root-cause analysis, problem-solving, and communication skills.
• Understanding of statistical process control and data analysis techniques for silicon yield improvement and quality metrics.
• Strong project management and cross-functional coordination skills.