What are the responsibilities and job description for the Lead Solutions Engineer - Runset Enablement (Physical Verification) position at Cadence Design Systems Inc?
Job Details
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are seeking a Lead Solutions Engineer specializing in runset enablement to support advanced semiconductor technologies. This role is critical for timely delivery of physical verification solutions by providing full-time coverage in the U.S. time zone. You will lead development and validation of Pegasus DRC and LVS runsets, collaborate with R&D on CCRs, and enable customer adoption through robust automation and best practices.
Key Responsibilities
Qualifications
Experience and Technical Skills
Behavioral Skills
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
We're doing work that matters. Help us solve what others can't.
We are seeking a Lead Solutions Engineer specializing in runset enablement to support advanced semiconductor technologies. This role is critical for timely delivery of physical verification solutions by providing full-time coverage in the U.S. time zone. You will lead development and validation of Pegasus DRC and LVS runsets, collaborate with R&D on CCRs, and enable customer adoption through robust automation and best practices.
Key Responsibilities
- Lead development and validation of Pegasus DRC and LVS runsets for advanced nodes.
- Architect automation frameworks for regression execution, issue detection, and validation reporting.
- Collaborate with R&D to resolve CCRs, influence product roadmap, and implement performance improvements.
- Provide technical enablement and support for customers on tool usage and advanced methodologies.
- Mentor junior engineers and establish best practices for runset development and QA.
- Work closely with internal teams to ensure timely delivery of verification solutions.
Qualifications
- MS degree with 5 years of experience or PhD with 3 years in Electrical Engineering, Computer Science, or related field.
- Strong understanding of semiconductor design and physical verification flows.
Experience and Technical Skills
- Proven expertise in developing and validating DRC and LVS runsets for Pegasus or similar tools (Calibre, ICV, Assura).
- Good-to-have: Experience with PERC and Fill runsets.
- Deep knowledge of advanced process technologies and methodologies (Ground Rules, SmartFill, ESD).
- Proficiency in scripting languages (TCL, Python, Perl) and Linux/Unix environments.
- Familiarity with chip fabrication processes and multi-die integration challenges.
- Experience in automation frameworks for regression and validation.
Behavioral Skills
- Strong leadership and mentoring capabilities.
- Excellent written, verbal, and presentation skills.
- Ability to influence cross-functional teams and drive strategic initiatives.
- Innovative mindset to explore unconventional solutions and optimize workflows.
- Operate with integrity and foster collaboration across global teams.
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
We're doing work that matters. Help us solve what others can't.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.