Demo

Physical Design Timing Engineer (STA)

Broadcom and Careers
San Jose, CA Full Time
POSTED ON 3/13/2026
AVAILABLE BEFORE 5/12/2026
Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job.
2. If you already have a Candidate Account, please Sign-In before you apply.
Job Description:
The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.
Key Responsibilities:
  • Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners
  • Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG)
  • Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies
  • Advanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA
  • Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments
  • Timing ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycle
  • Scripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.
  • Cross-Functional Collaboration: Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements
  • Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
  • Document best practices and lessons learned to drive continuous improvements in future projects
Qualifications:
  • Bachelor’s degree in Electrical Engineering or Computer engineering
  • A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
  • Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints
  • Well versed with scripting languages like TCL and Python, PERL, or Shell
  • Strong problem solving skills with attention to every technical aspect
  • Be a strong team player with clear and precise communication skills
  • EDA Tool Expertise: Expert proficiency in industry-standard sign-off tool
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $141,300 - $226,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Salary : $141,300 - $226,000

If your compensation planning software is too rigid to deploy winning incentive strategies, it’s time to find an adaptable solution. Compensation Planning
Enhance your organization's compensation strategy with salary data sets that HR and team managers can use to pay your staff right. Surveys & Data Sets

What is the career path for a Physical Design Timing Engineer (STA)?

Sign up to receive alerts about other jobs on the Physical Design Timing Engineer (STA) career path by checking the boxes next to the positions that interest you.
Income Estimation: 
$104,754 - $125,215
Income Estimation: 
$134,206 - $155,125
Income Estimation: 
$205,834 - $254,869
Income Estimation: 
$150,467 - $192,499
Income Estimation: 
$149,289 - $190,988
Income Estimation: 
$97,457 - $126,589
Income Estimation: 
$176,972 - $219,172
Employees: Get a Salary Increase
View Core, Job Family, and Industry Job Skills and Competency Data for more than 15,000 Job Titles Skills Library

Job openings at Broadcom and Careers

  • Broadcom and Careers Plano, TX
  • Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. 2. If you already have a Candidate Acc... more
  • 8 Days Ago

  • Broadcom and Careers California, CA
  • Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. 2. If you already have a Candidate Acc... more
  • 8 Days Ago

  • Broadcom and Careers San Jose, CA
  • Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. 2. If you already have a Candidate Acc... more
  • 9 Days Ago

  • Broadcom and Careers Jersey, NJ
  • Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. 2. If you already have a Candidate Acc... more
  • 15 Days Ago


Not the job you're looking for? Here are some other Physical Design Timing Engineer (STA) jobs in the San Jose, CA area that may be a better fit.

  • Chiparama San Jose, CA
  • Perform full-chip Static Timing Analysis (STA). Develop, validate, and own SDC constraints based on architectural and micro-architecture specifications. De... more
  • 17 Days Ago

  • Cadence Design Systems Inc San Jose, CA
  • At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are searching for a Software Engineer to w... more
  • 2 Days Ago

AI Assistant is available now!

Feel free to start your new journey!