Field-Programmable Gate Arrays Engineer

Job Title: Electrical/FPGA Engineer

Location: CEDAR RAPIDS, IA

Zip Code: 52498

Duration: 18 Months

Pay Rate: $63.66/hr.

Keyword's: #CEDARRAPIDSjobs; #Electricaljobs.

Start Date: Immediate

“We provide a competitive pay and benefits package. This position is offering a pay rate of $63.66/hr, however, Belcan considers several factors when extending an offer, including but not limited to education, experience, geographic location, and discipline. Benefits offered may include health care, dental, vision, life insurance; 401(k); education assistance; paid time off including PTO, holidays, and any other paid leave required by law.

Job Description:

Principal FPGA Engineer

Client is seeking a highly skilled and innovative Principal FPGA Engineering Contractor to work with our Applied Research and Technology (ART) Microelectronics Technology team. Your work will contribute to the development of cutting-edge defense solutions across Mission Systems, leveraging your expertise in the design, implementation, verification, and integration of a wide variety of high-performance digital FPGAs.

What You Will Do

• Adhere to all applicable Client Engineering Development and Quality processes, procedures, instructions and guidelines.

• Participate in Agile team meetings and planning activities, as required to support programs covered by this work plan.

• Requirements, design and verification of FPGA solutions • Integration of developed FPGA on target hardware units • Supporting peer reviews and certification analysis activities • Peer reviewing FPGA development artifacts • Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow • Contribute to engineering estimates for new program pursuits.

• Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status

Qualifications You Must Have

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience.

• A minimum of 5 years professional experience in FPGA development, ASIC front end, or related areas • Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.

• Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure • Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero).

• Strong debugging and troubleshooting skills for FPGA/ASIC systems.

• Proficiency with revision control concepts and tools (e.g., Git, Subversion)

Qualifications We Prefer

• Excellent communication and teamwork skills with the ability to work in a collaborative environment.

• Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet).

• Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog) • Experience in ASIC / FPGA lab validation using advanced laboratory equipment • Experience with Unix, scripting, C/C , and/or Perl