Manager Package Signal & Power Integrity (SIPI)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description:

As a Manager of Package Signal & Power Integrity (SIPI) at Astera Labs, you will lead and scale the SIPI engineering function responsible for developing high-performance IC packaging solutions that enable next-generation connectivity products. You will define technical strategy, build and mentor a high-performing team, and drive cross-functional execution from early definition through production. You will partner closely with silicon architecture, package design, PCB board team, hardware validation, manufacturing, and external suppliers (substrate vendors and OSATs) to ensure first-pass success while meeting electrical, cost, schedule, and production goals. You will also drive SIPI methodology evolution, modeling standards, and co-design frameworks across the chip–package–board ecosystem to enable scalable execution across multiple product lines.

Key Responsibilities

• Define and drive the company’s package SIPI strategy across multiple product generations. Ensure robust electrical performance for high-speed interfaces such as PCIe, CXL, Ethernet, and other SerDes protocols (200G/400G ).
• Lead packaging decisions impacting signal integrity, power delivery network (PDN) performance, and substrate design, including selecting packaging platforms, defining substrate stack-up, bump planning, and package architecture to meet high-speed and power integrity requirements.
• Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule.
• Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria.
• Build, mentor, and scale a high-performing SIPI engineering organization, establishing clear priorities, accountability, and technical excellence across concurrent programs while driving talent development and resource planning.
• Represent SIPI leadership in executive reviews and major program milestones, clearly communicating technical strategy, risks, tradeoffs, and execution status to senior leadership and cross-functional stakeholders.

Required qualifications:

• 10 years of progressive experience in Signal and Power Integrity (SIPI) modeling, analysis, and optimization across the chip–package–board system.
• Demonstrated experience leading teams or technical organizations in IC packaging environments.
• Strong ability to translate business objectives into technical roadmaps and execution plans.
• Deep expertise in EM extraction and modeling tools (e.g., ANSYS HFSS, SIwave, 3DLayout, Keysight ADS, etc.).
• Proven track record delivering high-performance packages such as FCBGA, FCCSP, coreless substrate, chiplet-based, and 2.5D architectures.
• Experience supporting high-speed connectivity products (PCIe, Ethernet, or equivalent SerDes technologies).
• Extensive experience in high-speed S-parameter extraction and system-level SI/PI modeling.
• Expert-level knowledge of PDN design including DC IR drop, loop inductance, target impedance, AC transient behavior, and chip-package-model (CPM).
• Experience driving chip–package–board co-design and system-level validation (eye diagram, ERL, transient response, power-aware SI).
• Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope).
• Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability.
• Experience leading vendor engagements and managing technical execution through production ramp.

Preferred Qualifications:

• Exposure to system-level performance considerations such as skew optimization, channel budget allocation strategy, or power delivery tradeoffs at the package level.
• Background in early package platform evaluation, technology benchmarking, and roadmap trade studies for next-generation connectivity or AI infrastructure products.
• Experience implementing modeling automation, workflow optimization, or data-driven design review processes to improve team scalability and execution efficiency.
• Experience with advanced packaging architectures including chiplet-based designs, 2.5D/3D integration, silicon interposer, bridge-based interconnect (e.g., EMIB-style), and heterogeneous integration platforms.
• Familiarity with UCIe-based die-to-die interconnect integration and associated SI/PI challenges at the package and substrate level.

This position can be hired as a Manager Level or Director Level. The base salary range is $230,000 USD – $265,000 USD. Your base salary will be determined based on location, experience, and employees' pay in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.