IC Packaging Technologist

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description

We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in 2.5D/3D integration, chiplet technology, fan-out wafer-level-packaging (e.g., FOWLP/FoCoS/Info), and heterogeneous integration. The successful candidate will lead strategic roadmap execution and scale innovative package solutions into production through close collaboration with OSATs, foundries and key suppliers

Basic Qualifications

• M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline.
• 10 years of experience in IC packaging development and NPI for high-speed SerDes and high-performance SoCs, ASICs, or memory products
• Deep hands-on expertise with FCBGA, fcCSP, co-packaged optics (CPO), and 2.5D/3D integration technologies such as CoWoS, RDL and silicon interposers, and chiplet-based architectures (e.g., BoW, UCIe); along with experience in fan-out wafer-level packaging (FOWLP/WLFO).
• Strong understanding of packaging material selection, substrate stack-up, bump/RDL design, and DFM for advanced nodes
• Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of tasks.
  
  

Required Experience

• Led multiple end-to-end advanced packaging NPI programs, from concept definition, pathfinding, design, supplier engagement, process development, and successful transition to HVM.
• Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G/448G PAM4.
• Experience defining RDL and bump architectures to enable die-to-die chiplet integration using interconnect standards such as BoW (Bunch of Wires) and UCIe (Universal Chiplet Interconnect Express).
• Demonstrated ability to lead collaboration with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development.
• Deep understanding of mechanical (e.g., warpage, CTE mismatch), thermal (e.g., heat dissipation, TIM), and electrical (e.g., parasitics, signal integrity) design trade-offs in advanced package development, with a proven ability to deliver robust and manufacturable packaging solutions.
• Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation.
• Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing teams.
  
  

Preferred Experience

• SI/PI knowledge is a plus: SI/PI concepts, S-parameter extraction, and PDN optimization using HFSS, SIwave, or Ansys Designer
• Knowledge of EDA design tools is a plus: Cadence Allegro/APD, Altium, etc.
  
  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ and non-binary people, veterans, parents, and individuals with disabilities.