What are the responsibilities and job description for the Design Verification Engineer position at ALKU?
LOCATION: On-site 5 days/week in Chandler AZ - LOCAL PREFERRED
DURATION: 6 Month Contract to Start
Design Verification Engineer
Role Overview
We are looking for an experienced DV Engineer to join the full-chip verification team working on one of the world’s largest and most advanced scientific / supercomputing SoCs – a many-thousand-core, RISC-V-based processor targeted at exascale-class HPC and AI workloads.
This is a true “cradle-to-grave” SoC verification role: you will own verification from initial bring-up through tape-out and post-silicon validation on Intel, AMD, and ARM-based server platforms.
Key Responsibilities
- Develop and execute full-chip verification plans using UVM testbenches for a 1536 × 64-bit RISC-V core design with integrated FPUs
- Own end-to-end protocol compliance (AXI, AFA, PCIe Gen5/Gen6, 16 G SERDES)
- Drive RISC-V ISA compliance using the official IFA (Instruction Fetch Accuracy) and RISC-V Architectural Test suites across all 1536 cores
- Heavy use of formal verification tools: JasperGold, VC Formal, Conformal LEC for equivalence and property proving at SoC level
- Build, debug, and maintain multi-billion-cycle emulation environments on Cadence Palladium and Synopsys Zebu
- Develop directed and constrained-random tests, checkers, scoreboards, and coverage closure at chip level
- Work closely with architecture, design, software, and platform teams to verify full Linux boot and scientific workload execution
- Lead bug triage, tracking (Git-based flow), and tape-out sign-off
Required Skills & Experience
- 7 years of hands-on DV experience with strong UVM methodology
- Proven track record of full-chip or large SoC-level verification (multi-core, high-speed IO, complex fabric)
- Expert-level with Cadence/Synopsys formal tools (JasperGold, VC Formal, Conformal LEC)
- Deep experience with Palladium or Zebu emulation platforms
- Strong protocol knowledge: AXI/AFA, PCIe Gen5/6, high-speed SERDES
- RISC-V verification experience (especially compliance and multi-core coherency)
- Scripting mastery: Python, TCL; solid C/C skills
- Familiar with Git-based bug tracking and modern CI flows
- Excellent debug skills on emulation and in post-silicon bring-up
- Prior experience on chips with 100 cores
- Contributed to official RISC-V International compliance submissions
- PCIe Gen6 or CXL verification experience