ASIC Design Engineer

Akkodis is seeking several full time ASIC Design Engineer's with our dedicated onsite team in the Boulder, CO area for a hybrid role (3x/week in office required). Candidates shall possess greater than 6 years of professional experience in RF/Analog/Mixed Signal layout design.

Starting Pay Range: $150,000 to $200,000 (salary commensurate based on experience and education levels).

ASIC Design Engineer job responsibilities include:

• Layout of cells, blocks, and chips in CMOS, BiCMOS, and Bipolar processes
• Chip-level assembly, verification, and debugging
• Planning and managing layout teams, including contractors and teammates
• Layout tool development and training
• Troubleshooting layout software and PDKs
• Project database management
• Driving top-down abstraction and black-box methodology

QUALIFICATIONS:

• Minimum 6 years of experience in RF/Analog/Mixed Signal layout design.
• Proficient in broadband RF/high-speed layout, sensitive RF analog matching, and parasitic minimization.
• Experience with PDKs and multiple foundry processes.
• Skilled in efficient chip, block, and cell floor planning and signal path optimization.
• Strong understanding of: Electromigration, Well-proximity and length-of-diffusion effects, Common-centroid matching, Differential pairs, Current mirrors.
• Comfortable with arrays, mirrored, and quadrature layouts.
• Expertise in RF, analog, and digital routing, physical verification, and database management.
• Familiarity with layout of: DAC/ADC, Broadband amplifiers, VGAs, Regulators, VCOs, PLLs, dividers, Samplers, Bandgaps, Charge pumps, IO/ESD structures.
• Strong understanding of RF, analog, digital, and mixed-signal fundamentals.
• Excellent communication and interpersonal skills
• Strong teamwork and leadership capabilities
• - Ability to mentor and collaborate across teams

CAD Tools:

• Cadence Virtuoso Schematic L, Layout L and XL.
• Physical Verification & Extraction: Cadence Assura, PVS, Pegasus, Mentor Graphics Calibre.
• Design Management: SVN, SOS, Synchronicity, IC Manage (or similar).

Programming/Scripting:

• Python, Ruby, Shell scripting is helpful though not required.
• P-Cell development helpful.

Bonus:

• Knowledge of Cadence Allegro PCB Design.

If you are interested in our ASIC Design Engineer role, please click EASY APPLY. For other opportunities available at Akkodis go to www.akkodis.com.

Equal Opportunity Employer/Veterans/Disabled

Benefits offerings include but are not limited to:

• Low-cost medical, dental, and vision premiums.
• 401(k) with match to help you plan for your future.
• Company-paid life insurance.
• Company-paid short-term and long-term disability insurance.
• Generous Paid Time Off (PTO) & Holiday Pay.

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit https://www.akkodis.com/en/privacy-policy.

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

· The California Fair Chance Act

· Los Angeles City Fair Chance Ordinance

· Los Angeles County Fair Chance Ordinance for Employers

· San Francisco Fair Chance Ordinance