Silicon Design Engineer - Memory/PHY (DDR/PHY)

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE

AMD is seeking a Silicon Design Lead to join a high‑performing team responsible for the design and development of complex silicon IP. This is an RTL design role focused on digital design for memory/PHY (DDR/PHY) subsystems, working across architecture, verification, and physical design to deliver high‑performance solutions.

THE PERSON

You are a highly experienced RTL design engineer with strong technical judgment and the ability to lead workstreams across a small team. You communicate clearly, collaborate effectively across organizations, and take ownership of complex design challenges.

You are comfortable providing technical leadership of a small team and driving execution, with the expectation that this role focuses on managing work. (with potential for future expansion based on performance).

KEY RESPONSIBILITIES

• Lead microarchitecture definition and RTL implementation of complex IP blocks and subsystems
• Develop high‑quality RTL and support verification, synthesis, and timing closure
• Analyze designs for performance, power, and area (PPA) and guide optimization decisions
• Collaborate closely with architecture, verification, and physical design teams to ensure successful integration
• Drive technical direction, design reviews, and engineering best practices across a small team
• Support debug, bring‑up, and silicon validation activities

PREFERRED EXPERIENCE

• Strong background in digital design and RTL development (Verilog/System Verilog)
• Required experience in DDR, PHY, or memory‑related design (a niche domain with a limited talent pool)
• Experience with complex SoC or IP design and integration
• Familiarity with synthesis, timing analysis, and end‑to‑end design flows
• Proven ability to lead technical workstreams or provide technical leadership
• Experience in Linux‑based development environments; scripting is a plus
• Experience from companies building PHY/DDR IP is strongly preferred (e.g., Intel, Synopsys, Cadence, Qualcomm, Microchip)

ACADEMIC CREDENTIALS

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (preferred)

LOCATION: Austin, TX

This role is not eligible for visa sponsorship.

#LI-MO2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.