Senior DFT Engineer (ASIC/Silicon)

Job Description

Our client is seeking a Senior DFT Engineer to support the development of advanced networking and photonic silicon solutions. This role is focused on implementing and validating Design-for-Test (DFT) methodologies to ensure highly testable, manufacturable, and reliable ASIC designs.

The ideal candidate will have strong experience with DFT architecture, implementation, and post-silicon validation, contributing throughout the full product lifecycle from pre-silicon development through production qualification and yield improvement.

Responsibilities

• Develop and implement DFT features for complex ASIC/SoC designs, including:
  • JTAG / Boundary Scan
  • Scan Insertion and Scan Compression
  • ATPG (Automatic Test Pattern Generation)
  • Memory BIST (MBIST)
  • Memory Repair
• Support DFT integration, verification, and signoff activities.
• Collaborate with design, verification, physical design, manufacturing, and product engineering teams throughout the silicon development lifecycle.
• Participate in post-silicon bring-up, debug, and validation activities.
• Perform failure analysis and root cause investigations to improve product quality, yield, and reliability.
• Contribute to production qualification and manufacturing readiness efforts.
• Help define and improve DFT methodologies, processes, and best practices.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5 years of experience in ASIC/SoC Design-for-Test (DFT) engineering.
• Strong hands-on experience with:
  • JTAG
  • Scan and Scan Compression
  • ATPG
  • Memory BIST (MBIST)
  • Memory Repair
  • Post-Silicon Debug and Validation
• Experience using:
  • Siemens Tessent
  • Cadence Xcelium
  • Cadence Genus
• Strong understanding of the ASIC development lifecycle from design through manufacturing.

Preferred Qualifications

• Experience developing and improving DFT methodologies from design through high-volume production.
• Knowledge of networking, optical, or photonic technologies.
• Strong debugging, analytical, and problem-solving skills.
• Ability to work effectively in a highly collaborative, cross-functional engineering environment.
• Strong attention to detail and system-level understanding of complex silicon products.

Desired Skills

DFT, JTAG, Scan, Scan Compression, ATPG, MBIST, Memory Repair, Tessent, Xcelium, Genus, ASIC, SoC, Post-Silicon Validation, Silicon Debug, Yield Analysis, Semiconductor Design.

Experience Level: Senior (5 years)

This is a Contract position based out of San Jose, CA.

The pay range for this position is $70.00 - $84.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following: • Medical, dental & vision • Critical Illness, Accident, and Hospital • 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available • Life Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term disability • Health Spending Account (HSA) • Transportation benefits • Employee Assistance Program • Time Off/Leave (PTO, Vacation or Sick Leave)

This is a fully remote position.

This position is anticipated to close on Aug 12, 2026.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.

San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.

Salary : $70 - $84